Hardware Implementation of 24-bit Vedic Multiplier in 32-bit Floating-Point Divider

摘要

Most of the Digital operations in computing systems performed by using Floating-Point (FP) arithmetic. FP multiplication is widely used arithmetic operation compared to addition, subtraction and division operations. Multipliers performed using Vedic technique shows higher speed of operation with better precision but it occupies slightly more area compared to conventional multipliers. In this paper, we implemented 24-bit Vedic multiplier using Urdhva-Tiryakbhyam (UT) technique with modified Carry Save Adders (CSA). The proposed high speed multiplier is used for calculating Mantissa part (24-bit) in single precision FP Division. This method outperform existing multipliers used for FP Division in terms of speed and accuracy. All the design parameters are evaluated using VIVADO synthesis tool and results are verified by simulation. The design was coded in Verilog HDL and is implemented in NEXYS 4 DDR FPGA kit.