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Design of low power RRAM cell using CNFET

机译:使用CNFET设计低功率RRAM单元

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This paper presents a CNFET based novel RRAM cell using memristor as memory element. The proposed RRAM cell is designed in such a way that half-select issue is resolved. Simulation results of critical design metrics of the proposed RRAM cell and previous 2T2M RRAM cell are compared. The proposed RRAM cell achieves 6.13x lower read delay along with 33x lower hold power due to use of MTCMOS power reduction technique than 2T2M cell at nominal VDD. It is a half-select free non-volatile RRAM cell with faster read operation and it is also power efficient.
机译:本文介绍了一种基于CNFET基于CNFET的新型RRAM单元,用作存储元件。建议的RRAM单元格以这样的方式设计,即半选择问题已解决。比较了拟议的RRAM细胞临界设计度量的仿真结果和先前的2T2M RRAM CELL。由于使用MTCMOS功率降低技术,所提出的RRAM单元达到6.13x较低的读取延迟以及33x较低的保持电源,其在标称VDD处的2T2M小区的使用MTCMOS功率降低技术。它是一个半选择自由的非易失性RRAM单元,读取操作更快,而且也是功率效率。

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