IMPLEMENTATION OF THE STANDARD FLOATING POINT MAC USING IEEE 754 FLOATING POINT ADDER

摘要

There are two types of processors. The first category is arithmetic processors and the second category is signal processing processors. For arithmetic processors in general precision is less where as for the signal processing processors precision is high because the signal is to be reconstructed at the receiving end. In the arithmetic processors the basic building block is Arithmetic Logic Unit (ALU). In the signal processing processors the basic building block is Multiplier Accumulator Content (MAC). For the Standard floating point MAC, more precision is essential compared with the traditional fixed point MAC because the former is to be designed by the IEEE 754 floating point arithmetic and the lateral is designed with fixed-point arithmetic i.e, the precision is limited to integer. But, in general if the precision is more, the accuracy is more. Hence, to improve the performance of the traditional fixed point MAC, in this work we implemented the standard floating point MAC using IEEE 754 floating point adder. This can be used to design all floating point DSP processors through the standard floating point MAC.