14 -bit Low Power Successive Approximation ADC using Two Step Split Capacitive array DAC with multiplexer switching.

摘要

The low power successive Approximation Analog to Digital converter (SA-ADC) is widely used in several applications mainly in bio-medical. In this paper, the performance of the 14 bit SAR–ADC analyzed through obtaining the power consumption by adopting the two split capacitive array DAC method. In addition to this, the area utilization and delay performance of two split DAC is also derived. The proposed two split capacitive array DAC with multiplexer switching, consumes the power of 12uW. So totally 190 times of power is reduced by the proposed method in comparison with conventional single split capacitive array DAC. Also this design requires 185 unit capacitances whereas the conventional design utilizes 256 unit capacitances in a capacitive array, thereby reducing the area of CDAC by 28%. In addition to this, the delay performance of the design also analyzed. Here design is made fully differential, hence the noise parameter is considerably reduced. Behavioral simulations were performed to check the effectiveness of design in each stage.