Disruptive Technology Elements, and Rapid and Accurate Block-Level Performance Evaluation for 3nm and Beyond

摘要

A new device architecture such as Forksheet emerges a promising candidate to the extension to Nanosheet. Yet, it is increasingly difficult to predict the power-performance accurately for the new architectures. We developed a fast and accurate power-performance methodology to predict block power-performance for 3nm and beyond nodes. This methodology was verified in imec's 2nm technology options such as Forksheet and semi-damascene BEOL processes. The results show excellent correlations with the performance-power gain of an ARM 64bit core.