An efficient software implementation of correctly rounded operations extending FMA: A + b + c and a × b + c × d

摘要

In its 2008 revision, the IEEE754 Standard for Floating-Point Arithmetic added the Fused-Multiply-And-Add (FMA) operation, computing a × b + c without intermediate rounding. This operation enables faster scalar products and doubled-precision arithmetic. The IEEE754 Standard is again undergoing revision. We propose an efficient software implementation of two additional operations: Fused-Multiply-Twice-And-Add, a × b + c × d and Fused-Add-Add a + b + c. Our implementation guarantees correct rounding in all rounding modes and IEEE754 compliant signaling. Although intended for reference purposes, with a 94 resp. 104 cycle latency, our software implementations are pretty fast.