A UVLO with zero static power consumption power-on reset circuit in HVIC

摘要

This paper proposes an Under Voltage Lock Out (UVLO) with zero static power consumption Power-on Reset (POR) circuit in a High-Voltage Integrated Circuit (HVIC). The HVIC with the proposed UVLO and POR circuit is fabricated using a 1.2 μm 650 V BCDMOS process. Experimental results show that the UVLO with POR circuit consumes very low static power; 411 μW at 15 V power supply. Moreover, the newly designed POR circuit works nicely regardless of high-side floating power supply rise time. The proposed circuit has good performance in terms of high-peak pulsating noise immunity. Therefore, this design is suitable for embedding in an HVIC with an integrated bootstrap diode for low power motor application and intelligent power modules.