A framework for system level low power design space exploration

摘要

Power management is a key feature in many digital systems, mainly those powered by battery. Introducing a power management strategy in a system should save power consumption while its functional performance must remain within application-dependent constraints. Designing such systems could be very challenging since power management impacts performance and the functional activity impacts power. The most convenient design level to address such challenge is at system transactional level where hardware and software could be described inside a single simulation model. Unfortunately, there are very few proposals that address the description at transactional level of both a power intent and a clock intent which constitute the low power specification entry required by RTL low power design tools. In this paper, we propose a framework able to describe graphically a power/clock intent and to generate automatically the associated simulation code. Adding this code as an overlay to the SystemC-TLM code of design allows a joined power/performance analysis of the whole system. Our framework provides an efficient support for low power design space exploration.