A Low Power Design Space Exploration Methodology Based on High Level Models and Confidence Intervals

摘要

Power consumption is nowadays a critical design constraint for circuits and systems. To efficiently guide early choices in the design flow, high-level estimations must be available. In order to address the different abstraction levels and the various targets, a global methodology is proposed here to elaborate suitable models. In this paper we are interested in exploring low consumption architectures in order to deduce that which meet(s) the constraints most. For this aim, several low power methodologies were established. They treat the energy consumption optimization problem at several levels especially on specific components like the hardware, or on the software, or on the communication or on the memory separately, and seldom on the whole system. However, as target architectures become complex, a global methodology that offers more efficient low power exploration becomes necessary. In fact, we propose a low power methodology based on rich performances models as well as a low power exploration technique. A complete model is proposed in order to deduce the total performances of the system according to the architecture and the application parameters. This model is used during exploration thanks to a technique based on simulated annealing. This technique makes it possible to exploit exploration according to several levels of granularity in order to be able to choose the level, which allows ensuring a precise and fast exploration. Moreover, an estimation frameworks and the mathematic approach are presented in this paper using a confidence interval.