A cell clustering technique to reduce transistor count

摘要

It is proposed a gate clustering technique to decrease the transistor count in a circuit. This enables an optimization willing to reduce area and power, specially leakage power. In a circuit netlist, some sets of connected cells with fanout one are clustered and replaced by a single cell with the same logic function, but with fewer transistors. To validate, we applied the technique to the ITC99 benchmark circuits synthesized to an 180nm vendor cell library. The results were compared with the original netlist regarding area, dynamic and leakage power. The number of transistors is reduced by 8 % in average, and the number of connections by 27 %. A significant power reduction is also achieved in function of the reduction of the transistor count.