Matching loading between sensing reference and memory cell with reduced transistor count in a dual-bank flash memory

摘要

A memory integrated circuit (100) includes a first bank (102) of memory cells and a second bank (104) of memory cells. A sensing circuit (114) is coupled to the first and second banks of memory cells to determine a data state of a selected memory cell in relation to a reference cell (118). A loading circuit (206) is coupled with a sensing circuit and associated with the reference cell to approximate loading associated with the selected memory cell. The loading circuit is shared for sensing memory cells of the first bank and memories of the second bank. By sharing the loading circuit, total device count and manufacturing costs where the memory integrated circuit are reduced.