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Package with simulation method to predict underfill flow pattern with different dispensed condition

机译:模拟方法包装,用于预测不同分配条件下的底部填充流型

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Currently electrical product is concerned about high function performance to meet consumer's requirement. Therefore, the package with high function feature is definitely required. The FCBGA (Flip-Chip Ball Grid Array) that provide the solution for low to high I/O, high electrical performance demand in high end memory, microprocessor applications where high frequency, high speed are required. The package offers pin counts in excess of 1800 with higher electrical performance compared to traditional BGA package. To develop the widest range of flip chip interconnect packages to meet consumer's demand is first target. In flip-chip packaging technology, the underfill encapsulation is one of the important processes to obtain a significant improvement in fatigue lifetime for the solder joints between IC chip and substrate. The advanced design of electronic devices aiming at the enhancement of the performance involves the increase of the number of solder bumps, smaller size of the IC chip and smaller gap height between IC chip and substrate. That leads to various problems caused by the flow behavior, such as voids in underfill process. In general, the product process engineer needs to take long time to do short-shot to find out well underfill flow pattern of dispensation parameter that balance flow pattern means underfill melt-front is with small difference gap between center and edge less than 10 bumps. Therefore, we want to use simulation skill to do underfill process prediction and find out good solution to provide well dispense parameter to control void issue and support product process engineer with underfill simulation result to reduce manpower resource. In this paper, we study FCBGA with die size as 22×20 mm and bump counts about more than 7000, and we compare different dispensation of three different I-pass lengths of 30%, 50%, 70% along die edge with different underfill weight (mg). We can observe underfill with different dispensation length and weight performs different underfill melt-front pattern and simulation results also correct with real underfill short-shot measurement.
机译:当前,电气产品关注高性能功能以满足消费者的需求。因此,绝对需要具有高功能功能的包装。 FCBGA(倒装芯片球栅阵列)为高端存储器,需要高频率,高速度的微处理器应用提供了从低到高I / O,高电气性能要求的解决方案。与传统的BGA封装相比,该封装提供的引脚数超过1800,并且具有更高的电气性能。开发最广泛的倒装芯片互连封装以满足消费者的需求是第一个目标。在倒装芯片封装技术中,底部填充封装是重要的工艺之一,可显着提高IC芯片与基板之间的焊点的疲劳寿命。旨在提高性能的电子设备的先进设计涉及增加焊料凸点的数量,减小IC芯片的尺寸以及减小IC芯片与基板之间的间隙高度。这导致由流动行为引起的各种问题,例如底部填充过程中的空隙。通常,产品工艺工程师需要花很长时间进行短时间查找,以找到分配参数良好的底部填充流型,即平衡流型意味着底部填充型熔体前沿的中心和边缘之间的间隙很小,小于10个凸点。因此,我们希望利用仿真技术来进行底部填充过程的预测,并找到良好的解决方案,以提供良好的分配参数来控制空隙问题,并为产品过程工程师提供底部填充的模拟结果,以减少人力资源。在本文中,我们研究了裸片尺寸为22×20 mm且凸点数约为7000的FCBGA,并比较了沿裸片边缘30 \%,50 \%,70 \%的三种不同I-pass长度的不同分配具有不同的底部填充重量(mg)。我们可以观察到具有不同点胶长度和重量的底部填充料会执行不同的底部填充料熔体前部模式,并且模拟结果也可以通过实际的底部填充料短时测量来校正。

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