Design and Test with Proton Beam of a 1.2 Gb/s Semi-custom Serialiser Implemented in 180 nm CMOS with SEU Mitigation by TMR

机译：使用TMR减轻SEU的180 nm CMOS中实现的1.2 Gb / s半定制串行器的质子束设计和测试

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This contribution describes the design of a semi-custom serialiser in 180nm CMOS technology. The design is verified for SEU immunity and BER with 30MeV protons.

机译：此文稿描述了采用180nm CMOS技术的半定制串行器的设计。该设计经过验证，具有30 MeV质子的SEU抗扰性和BER。

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《European Conference on Radiation and Its Effects on Components and Systems》|2017年|1-5|共5页
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Matteo Lupi; G. Aglieri Rinella; M. Bonora; H. Hillemanns; D. Kim; T. Kugathasan; A. Lattuca; G. Mazza; K. M. Sielewicz; W. Snoeys;
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Clocks; Radiation effects; Single event upsets; Semiconductor device measurement; Detectors; Phase locked loops; Current measurement;

机译：时钟;辐射效应;单事件干扰;半导体器件测量;检测器;锁相环;电流测量;

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机译：采用180nm CMOS技术的低功耗3位闪存ADC的设计与实现
2. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology [J] . Chatterjee B., Sachdev M. IEEE transactions on very large scale integration (VLSI) systems . 2005,第11期

机译：采用180nm CMOS技术的1.7GHz低功耗可延迟故障测试的32b ALU的设计
3. Design, implementation and measurement of a 120 GHz 10 Gb/s phase-modulating transmitter in 65 nm LP CMOS [J] . Noel Deferm, Patrick Reynaert Analog Integrated Circuits and Signal Processing . 2013,第1期

机译：在65 nm LP CMOS中设计，实现和测量120 GHz 10 Gb / s调相发射机
4. Design and Test with Proton Beam of a 1.2 Gb/s Semi-custom Serialiser Implemented in 180 nm CMOS with SEU Mitigation by TMR [C] . Matteo Lupi, G. Aglieri Rinella, M. Bonora, European Conference on Radiation and Its Effects on Components and Systems . 2017

机译：用180nm CMOS实现的1.2 GB / s半定制连续系的质子梁设计和测试，通过TMR缓解SEU缓解
5. Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process. [D] . Barlow, Matthew W. 2017

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6. A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications [O] . Muhammad Riaz Ur Rehman, Imran Ali, Danial Khan, 2021

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Design and Test with Proton Beam of a 1.2 Gb/s Semi-custom Serialiser Implemented in 180 nm CMOS with SEU Mitigation by TMR

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