Analysis and characterization of process/layout impacts on the performance of high-speed analog circuits

摘要

High speed analog circuits such as gigahertz analog-to-digital converters (ADCs) are key building blocks for various applications such as optical communication system and wideband oscilloscope. More design challenges need to be resolved by designers in designing such high speed analog circuits. Analysis and characterization of parasitic/process impacts are very important in helping the designers optimizing the circuit design. This paper will explore the impacts from process and layout parasitics on the performance of high-speed ADCs, by studying several important circuit parameters such as the sampling accuracy of the circuit, behavior of ESD protection capability and oscillation frequency of ring oscillators.