Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement

摘要

In this paper, a systematic design flow for asynchronous dual-rail encoded circuits with a high timing robustness level is introduced. With this flow, a synchronous Boolean network can be translated into its asynchronous counterpart consisting of the so-called dual-rail encoded functional modules (DRFMs). Each dual-rail encoded variable in the target asynchronous circuit is partially acknowledged, and the overall circuit satisfies speed independent requirements. The translation process is formulated within integer programing framework and solved with efficient algorithms. In addition, methods for designing DRFMs and characterizing their propagation delays are discussed, as well as simulation techniques used for performance analysis of the target asynchronous circuit.