Performance Analysis of Multifarious Programmable Gate Array Architecture for Vedic Multiplier

摘要

Momentous signal processing elements have been designed and developed using modern integration technologies. Higher frequency of data execution with lowest power utilization in highly optimized area are the primal antithetic expectancy of the modern applications from recent technology. In order to achieve such distinguished peculiarities, in many real-time processing applications, higher throughput arithmetic operations are important. Multiplication is historic arithmetic operations in such applications. With the revolutionary developments in the field of Programmable Architectures and Integration Technology, several FPGA devices are now a days available for prototyping. Through this creative writing, a detailed comparative study of the different Field Programmable Gate Arrays of Actel, Altera, Lattice, QuickLogic and Xilinx and have been conducted and presented the analytical outcome of the study, particularly for 32-bit Vedic Multiplier Architecture, implemented using concurrent Hardware Description Language. It is strongly essential to have cogent analysis of the FPGA performances which will be helpful to the numerous small and medium scale industry owners and first generation industrialists who are much inclined to stand in the market.