Optimized PIN devices by simulation

摘要

In order to increase the applicability of the PIN diodes for power engineering or telecommunications, different constructive variants of PIN diodes are investigated. The optimization of the PIN diodes continues in this paper with a processed doping compensation in the drift region to enhance the breakdown capability. The analyzed PIN structures are simulated by Athena-Atlas microelectronics software, to connect the technological flow to the electrical feature of the devices. The breakdown voltage increases from 218V for a simple PIN diode to 755V for a PIN variant with four p-well layers buried in the median I-region. The main limitation concerns the series resistance, during the forward biasing conditions.