Stability and accuracy analysis of power hardware in the loop system with different interface algorithms

摘要

The power hardware in the loop (PHIL) technology allows for testing a physical device under test (DUT) connected to the real time simulated rest of system (ROS) through a power electronic interface and interface algorithm (IA). Stability and accuracy questions remain open due to the non-ideal interface converter. This paper presents a frequency-domain stability analysis and a time-domain accuracy analysis of the PHIL system with different IAs, taking into account of the delay factors in the PHIL system. Results show that the damping impedance method (DIM) IA can realize a perfectly stable PHIL system, while the ideal transformer model (ITM) IA needs be modified to stabilize the PHIL system. The voltage and current expressions at both ROS side and DUT side are derived to make considerations about the accuracy of the PHIL system. Results show that matching of the waveforms at ROS and DUT sides can be achieved for passive DUTs with the DIM IA; however, for active DUTs, the matching suffers from the delay factors.