Design Of Experiment (DOE) For Thickness Reduction Of GaAs Wafer Using Lapping Process

摘要

This paper report a statistical method of performing wafer lapping experimental using Design Of Experiment (DOE) technique in order to get best lapping time to reduced thickness of GaAs wafer. Lapping speed, lapping time, oscillator speed and weight was selected as four main factor determine the shortest time of thickness reduction. A complete 2 4factorial of 4 factors (16 run) was design to determined the effect of selected factor. The lapping process was carried out using ULTRATEC Lapping& Polishing machine while the wafer thickness was characterized using Logitech non contact gauge. It was found that best lapping parameter was using lapping speed at 3 r.p.m, oscillator speed at 2 r.p.m and 3 weight block for duration of 240 sec. This parameter is able to reduce 156 驴m of wafer within 240 second without any crack problems and able to give good reference of reduction of GaAs wafer thickness process period