Fault coverage analysis of selection circuit based BIST for RF CP-PLL

摘要

Analog and mixed-signal testing is becoming an important issue that affects both the time-to-market and the product cost of many SoCs. In order to provide an efficient testing method for 865???870 MHz Charge pump phase-locked loop (CP-PLL) which constitutes a mixed-signal circuit a novel BIST method is developed. This BIST can be easily implemented with a test stimulus generator circuit, all existing blocks in CP-PLL and fault evaluation circuit. In order to reduce the chip area overheard, this technique use a selection circuit and one delay cell. The simulation results of the novel technique show high fault coverage 100% like that of our previous testing methods. Thus, it provides an efficient structural test suitable for a production test in terms of an area overhead, a test accessibility, and test time.