Cost effective realization of XOR logic in QCA

摘要

Quantum-dot cellular automata (QCA) has emerged as a promising and efficient nanoscale technology overcoming the demerits of the CMOS technology. With the rapid development in the field of nanotechnology, there has been an exponential increase in the practice of designing efficient logic circuits in the nanoscale era. However, it has always been a challenge for the designers to design a circuit meeting the requirements of a fast signal transfer mechanism and hence minimizing the delay to the lowest possible value. In this paper, a 5-input majority voter has been proposed which is used to synthesize an efficient 3-input XOR gate and XNOR gate. To find the significance of the proposed XOR gate, an efficient full adder as well as an odd and an even bit parity generator have also been implemented which shows significant improvement in terms of area, cell count and latency in comparison to the other previously proposed circuits.