Induced Gate-Source Voltage Mechanism and Gate Driver Design in All-SiC PWM Rectifier with Ultra-High Voltage Slew Rate (dv/dt)

摘要

Silicon carbide (SiC) power devices are fundamentally capable of operating at a higher switching speed than their silicon (Si) counterparts. However, the ultra-high voltage slew rate (dv/dt) aggravates the coupling effect between the two devices of the same phase-leg, leading to significant cross-talk issues. This paper reveals the driver parameters design method to suppress induced gate voltage spike and oscillation, without the penalty of increasing complexity and cost. The second-order dynamic system analysis derives the mechanism of the induced voltage spike and oscillation. Experimental results captured from a double pulse platform justified the second-order dynamic system analysis and spike and oscillation mechanism. Finally, the mechanism is used to guide the gate driver design of a 30kW commercial all-SiC PWM rectifier.