Design and Performance Analysis of Current Starved Voltage Controlled Oscillator

摘要

In this paper, current starved voltage controlled oscillators (CSVCO) using CMOS 180 nm technology are designed and their performances are evaluated. Then, a comparative study of different topologies of CSVCO like five-stage and seven-stage CSVCO is performed on the basis of power consumption, phase noise, center frequency, and tuning range. The simulation results reveal the better performance of the proposed design as compared to existing current starved VCO in terms of phase noise and power consumption.