This article deals with the clear analysis and experimental simulation results of the modified AES-128-bit algorithm which can be personalized. To improve this technique, we introduced the high-level increased parallelism scheme which will reflect even in Mi columns of the AES architecture. By using this technique, we can increase the throughput efficiency and is implemented on Quartus of FPGA device. With this technique, usage can increase the stack usage for 5% more with a minimum reduction of 30% area.
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