Design of Low-Power Binary Content Addressable Memory for Future Nanotechnologies

摘要

In today's industrial situation, there is a vast demand for devices with low power consumption. Therefore, the demand for reducing the power consumption in memory elements become vital as it occupies a significant portion of chip area. Content Addressable Memory is a kind of memory element used for search applications. The foremost CAM design requirement is to decrease power consumption connected with the huge amount of parallel active circuitry. In this work, a low-power Binary Content Addressable Memory (BCAM) design is implemented. The proposed CAM is simulated using Cadence Virtuoso simulator in 45, 90, and 180 nm technology. The proposed technique can be applied to nanotechnologies to reduce the power consumption without affecting the original functionality of the memory cell.