A CMOS self-biased 6.8 ppm/ºC area-efficient subthreshold voltage reference

摘要

A novel CMOS voltage reference, without any diodes or parasitic bipolar transistors is presented in this paper. The proposed circuit is based on the difference between gate-source voltages of high- and normal-threshold voltage nMOS transistors operating in subthreshold region. Without requiring any distinct bias circuit, the proposed circuit operates in a self-biased scheme resulting in a reduced chip area and lower power consumption. In a standard 0.18μm CMOS technology, the required chip area is about 0.002 mm. The generated reference voltage has a mean value of about 321 mV while achieving a temperature coefficient of 6.8 ppm/C from -40 to 120C. The circuit consumes 2.8 μA from a 1.8 V supply and indicates a line regulation of about 2.9mV/V when supply voltage varies from 1.2 V to 2 V. Without any filtering capacitor, the power supply rejection ratio is better than -50 dB at low and medium frequencies.