The Quantum-dot Cellular Automata represents one of the newest technologies that is emerging as possible replacement for CMOS. In this paper, we design a QCA serial adder (QSA) that leads to less cell count and area at no delay penalty. The latest proposed layout for QCA full adders, which uses a coplanar clock-zone based crossover design, is employed here. We further explore the design of serial-parallel multipliers based on the proposed QSA. Evaluations are based on the QCA-specific cost function and conventional measures, where the simulation results indicate that our designs achieve remarkable improvement in comparison to the best previous relevant works. Verification and simulations are carried out by QCADesigner.
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