digital signal processing chips; field programmable gate arrays; hardware-software codesign; microcontrollers; neural nets; Altera FPGA Cyclone III; FPGA based reconfigurable computing architecture; NI LabView Real-Time System; STM ARM32 microcontroller unit; analog neural network; analog sorting neural network; hardware implementation design; parallel sorting; signal processing; supervisory circuit; Computational modeling; Computer architecture; Field programmable gate arrays; Hardware; Mathematical model; Signal processing; Sorting; Analog neural network; FPGA hardware implementation; analog to digital converter; multicore system; reconfigurable computing architecture;
机译:用于模拟神经网络硬件实现的模块化T模式设计方法
机译:人工神经网络的模拟硬件实现
机译:用于硬件实现的神经网络的具有扩展存储时间的电流模式模拟存储器
机译:模拟排序神经网络的硬件实现设计
机译:机器学习硬件加速的新兴机会:从先进的神经网络实现,使用下一代技术实现超高效的深度学习框架
机译:尖峰神经网络有效硬件实现的概率尖峰传播
机译:用于模拟神经网络硬件实现的模块化T模式设计方法
机译:用于delta-backpropagation神经网络的模拟硬件