On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints

摘要

Power Optimal logic depth per pipeline stage has been explored in several papers in the literature. Simulation results on circuit models with inverters have shown that a logic depth per pipeline stage of 6 to 8 FO4 results in optimal power designs and can save good amount of power compared to a logic depth of 24 F04. In this paper we study power and logic depth trade off on ISCAS-85 benchmark circuits, considering flop, wave and hybrid pipelining architectures with supply and threshold voltage variations under gate size and area constraints. Towards the end we have developed a tool which can be used for designing power efficient digital combinational circuits with flop, wave and hybrid pipelining options under area and gate sizing constraints. We shows that, proper architecture selection results in power savings of 20-90% compared to the worst case power in the given range of logic depths. We also observe that the supply and threshold selection has savings of 10-85%. Our analysis shows that no denite conclusions can be made about logic depth per pipeline stage achievable for a circuit and it depends on the architecture, supply, threshold voltages and gate sizing range and permissible circuit area.