A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction

摘要

In this paper, we present a new approach to early error detection and correction based on dynamic timing error prediction and in-situ error correction. We demonstrate that monitoring distributed pipeline state dynamically and utilizing the inner property of instruction set architecture (ISA) such as instruction type or operand value can greatly improve the prediction accuracy with almost zero circuit penalty. In the event of a predicting timing error, an in-situ timing error correction mechanism borrows the timing of next pipeline stage, for register-based design. And it is the first time to apply an error resilient processor in near threshold voltage. This paper implements the approach on a CSKY-CK802 commercial processor in an in-house 0.6v smic40ll CMOS technology library. It reaches a 7-37% performance improvement with 74-87% prediction accuracy and 12-18% energy efficiency while incurring a 1.8% circuit area overhead over the traditional error resilient processor.