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From design-time concurrency to effective implementation parallelism: The multi-clock reactive case

机译:从设计时并发到有效实现并行性行为:多时钟反应盒

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We have defined a full design flow starting from high-level domain specific languages (Simulink, SCADE, AADL, SysML, MARTE, SystemC) and going all the way to the generation of deterministic concurrent (multi-threaded) executable code for (distributed) simulation or implementation. Based on the theory of weakly endochronous systems, our flow allows the automatic detection of potential parallelism in the functional specification, which is then used to allow the generation of concurrent (multi-thread) code for parallel, possibly distributed implementations.
机译:我们已经定义了从高级域特定语言开始的完整设计流程(Simulink,Scade,AADL,Sysml,Marte,Systemc),并一直到生成确定性并发(多线程)可执行代码(分布式) 模拟或实施。 基于弱代价系统的理论,我们的流程允许在功能规范中自动检测潜在的并行性,然后用于允许生成并行(多线程)代码进行并行的,可能的分布式实现。

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