后端实现时几种减小时钟延迟的有效方法

摘要

主要探讨在嵌入式芯片后端设计时怎么实现时钟延时最小时钟网络。时钟网络优化的障碍可能来自很多方面，主要包括以下三个方面：不同转换率的输入输出单元，具有大负载电容端口以及来自不同时钟域的时钟网络。针对提出的问题，讨论一般采取的解决方案，优化时钟延时，通过针对性的方法技巧，可以在时钟树自动综合时有效地减少时钟树延时。%The paper mainly discusses the clock latency is how to achieve the minimum clock network in SOC IC backend design. The clock network optimization barriers may come from many aspects, this paper discussed mainly includes the following three aspects: I/O cells with different conversion rate, high load capacitance pin and from different clock domains of clock network. For those problems, the paper will discuss solutions generally taken, optimization of clock latency, through targeted skills, can effectively reduce the clock tree latency in clock CTS.