A multi-mode energy-efficient double-precision floating-point multiplier

摘要

Energy-efficiency is among the most important goals of the current IC industry. To achieve this goal each subcomponent of a chip must be optimized for energy). Even though a tremendous amount of research has been dedicated to optimizing floating-point multipliers (FPM) for better performance, efforts are continuously being made to further enhance them, indicating their importance in the computing world. Hence a multi-mode operating energy-efficient FPM is introduced in this work. This double-precision multiplier dynamically adapts to three modes of operations based on the effective precision of the inputs: low-precision, asymmetric, and full modes, where a 24×24, 24×53, or 53×53 fraction multiplication is required, respectively. Due to the highly frequent occurrence of low-precision operands (i.e., the least significant bits of the fraction are zeros), switching between these modes saves energy by avoiding unnecessary bitlevel computations. Results show up to 25% and 21% savings in dynamic energy and total energy, respectively. A two-tier 3DIC FPM design is also proposed to further enhance the performance of the multi-mode FPM.