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A novel methodology for wafer-specific feed-forward management of backside silicon removal by wafer grinding for optimized through silicon via reveal

机译:用于通过晶圆研磨进行背面硅去除的特定于晶圆的前馈管理的新方法,以优化硅通孔显示

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As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness and the final via reveal process. It can compensate for poor via fabrication depth uniformity and less than ideal temporary bonding total thickness variation (TTV). In this paper we will demonstrate the utility of two tools that when used together can systematically produce thin TSV containing wafers to their optimal thickness while protecting the wafers from particulate contamination. The first instrument in this process scheme is a metrology tool that utilizes IR reflectance to measure the silicon thickness remaining between the bottom of the TSV and backside surface of the wafer. These measurements are then transferred to a special grinding tool that can interpret the data and make changes to the grinding depth within the wafer so as to leave thickness of silicon above the TSVs as uniform as possible. Having removed the bulk of the Si through mechanical grinding and Chem/Mech polishing, the next step in the via-middle process is to remove the last few microns of Si overburden to expose the vias. By leaving a shallower Si layer above the TSV during the thinning process compared to current process, the final via reveal process time can be reduced. Also the need for rework in this process because of the wafer-to-wafer variability in the remaining silicon thickness above the TSV can be eliminated. In addition to measuring the pre-grinding Si thickness, the IR reflectance measurement tool can be used to verify the remaining silicon thickness post grind, establishing thinning process feedback and via reveal process feed-forward data.
机译:随着具有直通硅通孔(TSV)的3DIC接近批量生产准备工作,精密背磨的重要性变得越来越明显。主动管理背面研磨工艺具有多个优势,因为它减少了由于过早接触过孔而导致晶片背面污染的风险,可以优化薄化后的残留硅厚度和最终的过孔显示工艺。它可以补偿通孔制造深度均匀性差和小于理想的临时粘合总厚度变化(TTV)的情况。在本文中,我们将展示两种工具的实用性,当将它们一起使用时,可以系统地生产出包含薄硅通孔的薄晶圆至最佳厚度,同时保护晶圆免受颗粒污染。此工艺方案中的第一台仪器是一种计量工具,该工具利用IR反射率测量残留在TSV底部和晶圆背面之间的硅厚度。然后将这些测量值传输到专用的研磨工具,该工具可以解释数据并更改晶片内的研磨深度,以使TSV上方的硅厚度尽可能均匀。通过机械研磨和Chem / Mech抛光去除了大部分Si之后,通孔中间工艺的下一步是去除最后几微米的Si覆盖层以暴露通孔。与当前工艺相比,通过在减薄工艺期间在TSV上方保留较浅的Si层,可以减少最终的过孔显示工艺时间。由于在TSV之上的剩余硅厚度中晶片之间的差异性,也可以消除在该工艺中对返工的需要。除了测量预研磨的硅厚度之外,红外反射率测量工具还可用于验证研磨后的剩余硅厚度,建立减薄过程反馈并通过揭示过程前馈数据。

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