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A stress-based effective film technique for wafer warpage prediction of arbitrarily patterned films

机译:基于应力的有效成膜技术,用于任意图案化膜的晶片翘曲预测

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Initially flat silicon wafers are prone to warp due to the high levels of intrinsic stress of deposited films, particularly metallic films. Processing and handling of warped wafers in the fab is a challenge. One of the ways to control the degree of warpage is by limiting the amount of metallization allowed on the wafer. However, this imposes a constraint on the silicon designers, and can lead to decreased performance of the IC. Therefore, there is a need to accurately predict the amount of wafer warpage caused by a proposed layout in order to give designers the most freedom to develop IC solutions while ensuring that the processed wafers meet the manufacturing equipment requirements. The metal artwork (in addition to other materials, layer thicknesses, processing parameters, etc.) is an important factor in determining wafer curvature. Simple analytical methods, such as Stoney's Formula, cannot capture the non-uniform warpage due to these patterned films. On the other hand, numerical methods which require detailed modeling of the film patterns across the whole wafer are computationally expensive. Thus, a new finite element modeling technique was developed in which the entire patterned film stack is represented as a uniform effective orthotropic film bonded onto a silicon substrate. The orthotropic properties are determined from a small set of virtual experiments using a unit-cell model that is characteristic of the actual pattern. The resultant effective film, despite using a very course mesh, is able to capture the non-uniform surface stress induced by a patterned multi-layer film stack, and thus results in very similar wafer warpage as in the conventional detailed model. Several example film patterns will be presented here, where the warpage difference between the detailed model and the effective film model are less than a few percent across the whole wafer.
机译:由于沉积膜,特别是金属膜的高固有应力水平,最初的平面硅晶片容易翘曲。在晶圆厂中处理和处理翘曲的晶圆是一个挑战。控制翘曲程度的一种方法是限制晶片上允许的金属化量。但是,这对硅设计人员造成了限制,并可能导致IC性能下降。因此,需要精确地预测由所提出的布局引起的晶片翘曲的量,以便给予设计者最大的自由来开发IC解决方案,同时确保所处理的晶片满足制造设备要求。金属图稿(除了其他材料,层厚度,加工参数等)是确定晶圆曲率的重要因素。由于这些图案化的薄膜,简单的分析方法(例如,斯通尼公式)无法捕获不均匀的翘曲。另一方面,需要对整个晶片上的薄膜图案进行详细建模的数值方法在计算上是昂贵的。因此,开发了一种新的有限元建模技术,其中将整个图案化的薄膜叠层表示为键合到硅基板上的均匀有效的正交各向异性薄膜。正交各向异性特性是使用一小组实际模型的特征,通过一小组虚拟实验确定的。尽管使用非常平整的网格,所得的有效膜仍能够捕获由图案化的多层膜叠层引起的不均匀的表面应力,并因此导致与常规详细模型中非常相似的晶片翘曲。这里将展示几个示例性的膜片图案,其中详细模型和有效膜片模型之间的翘曲差异在整个晶圆上小于百分之几。

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