Vector-Based Mismatch Shaping circuit for a low IF Multibit ΣΔ ADC

摘要

This paper shows the design of a mismatch shaping circuit to improve the linearity of a multibit bandpass ΣΔ ADC whose center frequency is f_s/32. For such low IF ADC, the Data Weighted Averaging algorithm is not efficient as the notch of shaped quantization noise is not close enough to DC. On the other hand, an N-path transformation using N=32 is only efficient for very narrow bandwidths due to increased noise power in the lobes adjacent to the targeted notch. A vector-based mismatch shaping circuit implementing a notch filter has been designed to provide the desired bandpass mismatch shaping. The design has been described in VHDL and synthesized in 180nm CMOS process. A switch matrix based Data Weighted Averaging circuit has been also designed in the same process to compare speed and performance.