Gate chain structures with on-chip clock generators for realistic high-speed dynamic stress

摘要

NAND and NOR gate chains including on-chip frequency variable clock generators are presented as a way of evaluating hot-electron-induced degradation of CMOS performance under realistic high-speed dynamic stress. Dual gate chains with a common input clock are suitable for measuring net gate delay time by subtracting the delay times of the two chains with different numbers of stages. Operating gate chains at higher frequencies and elevated supply voltages accelerates hot-electron-induced degradation of circuit performance to yield useful information for estimating lifetimes under normal-use conditions and realistic dynamic stress. Aluminum NAND gate chains with aluminum interconnect line loads are also suitable for estimating electromigration failure of aluminum lines in actual circuits through high-frequency operation and elevated temperature.