Correlation study Of spatial ESC temperature profile and optical CD/CD SEM measurements to investigate silicon recess and gate CD after etch

摘要

The gate module comprises arguably some of the most critical process steps in 28nm semiconductor device manufacturing. One key step involved is the final gates etch. Typically all chip manufacturers dedicate a large part of their metrology capacity to the control of related device-limiting process steps. Most importantly the gate length at the bottom of the polysilicon line needs to be controlled very tightly. But given the challenging requirements in carrier density engineering more and more attention is paid to the area located next to the actual gate line. The etch process if not very well monitored and controlled can cause loss of active silicon very often denominated as a recess into the silicon. A loss of material even in the Angstrom range will affect device performance. Should this step be out of specification, it will adversely affect saturation drive current (ID SAT) by reducing the charge carrier density in source and drain regions, leading to degraded device performance [1]