A double-sampling cross noise-coupled split ∑△-modulation A/D converter with 80 dB SNR.

摘要

This paper presents the design of a double-sampling split ∑△-modulation analog-to-digital converter with cross noise-coupling. Double-sampling is used to achieve high conversion speed and low power consumption. To tackle the problem of quantization noise folding due to path mismatch, a fully floating bilinear integrator is used. Then the quantization noise is cross-coupled between two identical ∑△-modulators. This increases the effective noise shaping order of this structure with one. The final design is an optimized second order double-sampling split ∑△-modulator with third order noise shaping through cross noise-coupling. This design is simulated at transistor level in an 0.18-μm CMOS process for 80 dB SNR and 5 MHz bandwidth.