An All-Digital Architecture for Low-Jitter Regulated Delay Lines

摘要

A bang-bang delay-locked loop based on a digital filter and a DAC controlling the line delay suffers from the presence of a limit cycle that produces periodic jitter. A tight trade-off exists between jitter and DAC resolution. This paper proposes an all-digital architecture of regulated delay line based on a digital first-order △∑ modulator and a single-bit DAC, which eliminates the need for the high-resolution DAC and trades jitter against bandwidth. A theoretical estimation of the jitter induced by the △∑ quantization noise is provided. The realized delay-locked loop generates 16 phases of the 3-4 GHz input signal in a 90-nm CMOS technology. The simulated delay jitter of 30 fs rms confirms the theoretical estimation.