field programmable gate arrays; floating point arithmetic; hardware description languages; iterative methods; logic design; FPGA based single precision iterative floating point multiplier; Verilog description language; educational use; sequential binary multiplication procedures; shift and add multiplication; Adders; Algorithm design and analysis; Central Processing Unit; Computer architecture; Computers; Education; Field programmable gate arrays; Educational Design; Floating Point Multiplier; Iterative Implementation; Single Precision IEEE 754;
机译:具有SIMD支持的低功耗多精度迭代浮点乘法器
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机译:基于FPGA的单精度迭代浮点倍增器,用于教育用途
机译:IEEE 754单精度浮点快速傅立叶变换的硬件架构的低功耗同步设计。
机译:可逆单精度浮点减法器的设计
机译:使用VHDL在Spartan上的单精度浮点倍增器的设计与实现