Multiplier capable of calculating double precision, single precision, inner product and multiplying complex numbers

摘要

An AND gate (7A) inputs the most significant bit of a lower word (Y3-0) of an multiplicand or "0" to an input terminal of the least significant bit of Booth's decoders (1A and 1B) to which an upper word (Y7-4) of the multiplicand is inputted based on a control signal (S1). An AND gate (7B) replaces a part (P03 to P00, P13 to P10) of a partial products with "0" based on the control signal (S1). A selector (10) replaces other part (P28 to P25, P38 to P35) of the partial products with partial products (P24 and P34) of the lower bits than the other part of the partial products. Whereby, a plurality of pairs of data can be multiplied at one time. IMAGE