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Smart-hopping: Highly efficient ISA-level fault injection on real hardware

机译:智能跳跃:在真实硬件上的高效ISA级故障注入

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Fault-injection experiments on the instruction-set architecture level are commonly used to analyze embedded software's susceptibility to hardware faults, typically involving a vast number of experiments with systematically varying fault locations and times. Determinism and high performance are the predominant requirements on fault-injection platforms. Injecting faults into a real embedded hardware platform instead of a simulator is favorable for both workload execution speed and result accuracy. The most performance-critical part of such a fault-injection platform is the “fast forward” operation, which executes the target machine code without faults until the exact dynamic instruction is reached at which the execution must be stopped to inject the next fault. Unfortunately, most embedded CPUs do not support this operation efficiently. In this paper we present an approach that speeds up fast-forwarding significantly for most workloads with minimal requirements on hardware support. Based on a previously recorded instruction trace — which is needed for systematic fault-injection experiment planning anyways — we use standard debugging hardware to advance to a chosen point in program execution with a minimal number of steps. We evaluate our FAIL∗ tool platform with two MiBench benchmark categories, and improve experiment throughput by up to several magnitudes compared to similar fault-injection tools in the field.
机译:指令集架构级别的故障注入实验通常用于分析嵌入式软件对硬件故障的易感性,通常涉及具有系统变化的故障位置和时间的大量实验。确定性和高性能是对故障注射平台的主要要求。将故障注入真正的嵌入式硬件平台而不是模拟器,有利于工作负载执行速度和结果准确性。这种故障注入平台的最具性能关键部分是“快进”操作,它执行目标机器代码而不会发生故障,直到达到确切的动态指令,必须停止执行以进入下一个故障。不幸的是,大多数嵌入式CPU不高效支持此操作。在本文中,我们提出了一种对大多数工作负载的最大值快速转发的方法,对硬件支持最小的要求。基于先前录制的指令迹线 - 无论如何都是系统故障注入实验规划所需的 - 我们使用标准调试硬件在程序执行中使用最少的步骤执行。我们使用两个Mibench基准类别评估我们的失败*工具平台,并通过与现场类似的故障注入工具相比,通过多个大小提高实验吞吐量。

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