Implementation of direct frequency synthesizer for multiple frequency clock generation

摘要

This paper presents a low-jitter and high output frequency resolution direct frequency synthesizer (DFS) with phase interpolator (PI) based fractional divider (PIFD) for multiple frequency clock generation. Compared to conventional DFS, the proposed architecture offers higher frequency resolution, higher maximum frequency, better phase noise and jitter performance, as well as higher switching speed. In this paper, the fundamental jitter limitation of the synthesizer, due to the PI non-linearity and device mismatch, is analyzed in detail. It is shown that the PI non-linearity increases exponentially with the input signal intersection angle. In addition, the jitter from VCO is also taken into account. Designed and simulated in a 65nm CMOS technology, the frequency synthesizer provides a wide frequency range from 8MHz to 8GHz, with frequency resolution 8MHz. The maximum switching time is limited by the output clock period. The best RMS jitter is 3ps @ 8GHz when NpI=0 and the worst-case RMS jitter is 12ps @ 7.994GHz when NpI=35. The spurious free dynamic range is 56dBc in worst case.