A Low Power Residue Amplifier using Incomplete Settled Differential Flipped Voltage Follower

摘要

This paper presents a differential flipped voltage follower (DFVF) residue amplifier (RA) with the CMOS input pair for the pipeline-SAR ADC. The current reuse technology, incomplete settled and dynamic characters achieve a high power efficiency with a large linear range. The effect gain is insusceptible to clock jitter with the range of ± 1.05ps and can be compensated at different temperatures though trimming tail voltage bias. The prototype RA is designed in 28nm CMOS process, achieving 8.3 gain in 220ps amplification time and consuming only 0.644mW under 0.9-V supply.