A Fast Settling Low Noise Ring Amplifier for High Speed Pipelined SAR ADCs

摘要

In this paper, a fast-settling ring amplifier (ringamp) with high linearity and low noise is presented. Implemented in 40 nm CMOS technology, the ringamp is shown to meet the requirements of residue amplifiers used in pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs). A modified common mode feedback (CMFB) loop makes the amplifier robust enough to work well over all process corners, which solves the long-existing problem in traditional ringamps. Simulation results show that signal to distortion ratio (SDR) is above 50 dB in various temperature/corner conditions.