Towards formal verification of reset sequence in fully asynchronous digital circuits

摘要

We propose a method for the formal reset sequence verification for digital asynchronous circuits. First the traditional approach for the reset verification is discussed and the need for a novel solution is shown. The proposed method is based on the extension of the standard logic types with a multi-value logic type and a source code instrumentation method. The method is finally applied to an exemplary circuit fragment showing promising results.