Level oriented formal model for asynchronous circuit verification and its efficient analysis method

摘要

Using a level oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model data-path circuits. On the other hand, in order to use such a model for a little larger circuit, some technique to avoid the state explosion problem is essential. This paper first defines one level oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation with guaranteeing the correctness of the verification.