SRAM chips; elemental semiconductors; low-power electronics; network-on-chip; silicon; Si; adaptive bandwidth networks; application traffic; average traffic; drowsy SRAM cells; false VC activation elimination; large-scale chips; on-chip network; power budgets; power consumption; risk degrading performance; silicon defects; static power overheads; static power reduction; variable-width datapath; virtual channels; worst-case traffic loads; Bandwidth; Benchmark testing; Clocks; Delays; Logic gates; Ports (Computers); Resource management;
机译:大型片上电网网络的变分归约统计分析
机译:矩形片上网络的静态形状和核心映射选择
机译:具有不均匀功耗和块间去耦电容的IC中片上配电网络的电源噪声和阻抗
机译:用于片上网络静电减少的可变宽度数据路径
机译:使用等待时间插入方法对不规则芯片上配电网络中的电源噪声进行瞬态仿真,并对以频带有限的数据为特征并由任意端接终止的互连进行因果瞬态仿真。
机译:具有静态和动态条件的MEMS-IMU降噪的混合深复发神经网络
机译:用于片上网络静电减少的可变宽度数据路径