A combinational logic implementation of S-box of AES

摘要

This paper presents a combinational logic based Rijndael S-box implementation for the SubByte transformation on ASIC. Combinational implementation of S-box results in low cost, small area occupancy and high throughput as compared to the typical ROM based lookup table implementation with fixed and unbreakable access time. S-box has been implemented using 0.18µm CMOS standard cell library at 1.62V and runs at clock frequency of 71.43MHz. We could achieve throughput of 571.5Mbps with core utilization of 85%, core area occupied is 39.88.4µm2 using only 178 cells. Total power dissipation of the S-box implementation is 0.611mW which is quite lower than other literature available.